Field of Invention
The present invention relates to a system and method for substrate processing, and more particularly to critical dimension trim method for patterning during one or more stages of processing a structure pattern in a substrate.
Description of Related Art
This invention relates to structure patterning using a plasma trimming process. In a typical method of making a pattern on a substrate, a stack of various materials are deposited and the substrate then goes through the lithographic process where resist is coated onto the substrate and exposed to make a pattern. The resist pattern is then transferred to the underlying layers through a succession of plasma steps. To those familiar in the current art, two schemes are commonly used to pattern a substrate. The first scheme involves deposition of optical planarizing layer (OPL), typically a spin-on material followed by deposition of silicon anti-reflective coating (SiARC), also spin-on, followed by resist coating and lithographic processes. In another scheme, deposition of amorphous carbon layer using CVD deposition, SiON film deposition using a CVD process, bottom anti-reflective coating (BARC) deposition where the BARC utilizes a spin-on process, followed by a resist coating and a lithographic process. Control of the critical dimension (CD) throughout the etching of each of these layers is important and several methods/strategies have been used to achieve a final target CD.
There are several possibilities of results regarding the final target CD. The first case is where the final CD target is the same as the printed CD target, meaning the opening of the SiARC/OPL/underlying layers needs to have a 0 bias impact on the CD. The second case is one where the final CD target needs to be smaller than printed CD, a fairly common occurrence as industry is moving to smaller nodes and the EUV process is still currently not at a “manufacturable state”. A third case is when the final CD target is too small compared to the printed CD target. A final pattern in the third case may have unacceptable line edge roughness (LER)/line width roughness (LWR) values. In extreme cases, the structure pattern may experience collapse and make the substrate unusable. This invention relates to the second and third cases. Since there are multiple stages in the integration scheme where CD trimming can be done, there is a need for an approach where the final target CD is most likely to be within an acceptable target CD range. Alternatively, a strategy of completing the required CD trimming can also be implemented.